Digtal-to-analog converter and method for reducing harmonic distortion in a digital-to-analog converter

ABSTRACT

The invention relates to a digital-to-analog converter. In order to reduce distortion in the output, the converter comprises a first and a second current output (OUT, XOUT), at least two current sources ( 1 ) and assigned to each of the current sources ( 1 ) a current switch circuit. Each current switch circuit comprises means ( 4, 5, 6, 7 ) for creating two overlapping complementary control signals out of a signal indicating whether the current source ( 1 ) is selected, while in a first group of the current switch circuits the connection of the current source ( 1 ) to the current outputs is controlled by one of the control signals respectively, and while in a second group of the current switch circuits the control by the control signals is exchanged, each of the current switch circuits of the second group comprising in addition means ( 10 ) for inverting the signal input to the means for creating two overlapping complementary control signal ( 4, 5, 6, 7 ).

FIELD OF THE INVENTION

[0001] The invention relates to a digital-to-analog converter and to amethod for reducing harmonic distortion in a digital-to-analogconverter.

BACKGROUND OF THE INVENTION

[0002] Digital-to-analog (D/A) converters are used in a variety ofapplications for converting digital signals into corresponding analogsignals. They are employed for example in base stations and in radiorelay transmitters. The purity of the analog output signal is often ofgreat significance for the performance of the application.

[0003] In current-steering D/A converters, the analog output signal isformed by connecting a number of current sources to a current output. Inmost of the applications, each current source is steered to one of twocurrent outputs, resulting in a differential output signal current.

[0004]FIG. 1 shows as an example a segmented current steering 10-bit D/Aconverter with a 6-bit MSB (most significant bits) block formed of 63unweighted current sources 1 and a 4-bit LSB (least significant bits)block formed of four binary-weighted current sources. To each currentsource there is assigned a differential switch pair S controlled by acurrent switch circuit and used to steer the respective current sourceto one of two current outputs OUT and XOUT. The four current sources ofthe LSB block output a one-, two-, four- and eight-fold predeterminedcurrent respectively if selected, thereby enabling an output of 8different current values. Each of the current sources of the MSB blockoutputs a 16-fold predetermined current if selected. Each current sourceof the MSB block is responsible for a stepwise increase of the outputcurrent signal by a 16-fold predetermined current 16I when selected,thereby enabling an output of 64 different current values. The currentsof the MSB and the LSB blocks are summed to form the output signal.

[0005] Today it is possible to design an integrated current steering D/Aconverter for sampling frequencies of up to several hundreds ofmegasamples per second with a resolution of up to 14 bit. However, withresolutions of 10 bit or more, the full resolution bandwidth is limitedto several megahertz. In telecommunications applications a signalbandwidth of several megahertz is required.

[0006] The limiting factor for an effective resolution with highfrequency signals is distortion. Timing errors and code dependency ofthe output impedance contribute to distortion. The most common cause ofdistortion, however, is asymmetrical glitches that occur during thestate changes in the differential switches. If the resolution of a D/Aconverter is equal to or more than 10 bit, distortion starts to limitthe dynamic linearity rapidly after some critical point of usually lessthan 10 MHz.

[0007] For illustration, FIG. 2 shows a simulated spectrum of the D/Aconverter of FIG. 1, the output voltage V_(out) being depicted over thefrequency f/Hz of the outputted signal. The used sampling rate is 200MHz and the signal frequency 20 MHz. Even though the output signal isdifferential, the even order harmonic components are high. The 2^(nd)order harmonic limits the SFDR (spurious free dynamic range) to 53 dB.This illustrates that the differential output is not symmetrical inpractice.

[0008] Attempts to improve the spectrum are known from the state of theart. Most published methods focus on decreasing the glitch energy inorder to improve the spectral purity, but the 2^(nd) harmonic componentcan still appear in the spectrum. Moreover, the 2^(nd) harmonic usuallydominates the distortion. Such methods are described for example inAnalog Devices AD9754 Datasheet: “14-bit, 125MSPS High Performance TxDACD/A Converter”, Analog Devices, Inc., 1999; J. Bastos, A. M. Marques, M.S. J. Steyaert, W. Sansen: “A 12-bit Intrinsic Accuracy High-Speed CMOSDAC”, IEEE J. Solid-State Circuits, vol. 33, no. 12, December 1998, pp.1959-1969; J. Vandenbussche, G. Van der Plas, A. Van den Bosch, W.Daems, G. Gielen, M. Steyaert, W. Sansen: “A 14-bit 150 MSamples/sUpdate Rate Q² Random walk CMOS DAC”, Proc. IEEE Int. Solid-StateCircuits Conf., February 1999, pp. 146-147; and A. Van den Bosch, M.Borremans, J. Vandenbussche, G. Van der Plas, A. Marques, J. Bastos, M.Steyaert, G. Gielen, W. Sansen: “A 12-bit 200 MHz Low Glitch CMOS D/AConverter”, Proc. Custom Integrated Circuits Conference, 1998, pp.249-252.

[0009] Another proposed possibility is to use track-and-hold circuitryin the output, as disclosed in A. R. Bugeja, B.-S. Song, P. L. Rakers,S. F. Gilling: “A 14-bit 100 MSamples/s CMOS DAC Designed for SpectralPerformance”, Proc. IEEE Int. Solid-State Circuits Conference, February1999, pp. 148-149 and A. Bugeja, B.-S. Song: “A Self-Trimming 14 b 100MSample/s CMOS DAC”, Proc. IEEE Solid-State Circuits Conference,February 2000, pp. 44-45. The settled signal from the output is trackedso that the state change phase cannot be seen in the output signal. Theusage of a track-and-hold circuit in the output increases the complexityof the D/A converter and the current consumption and is not verypractical in mobile terminal units. In addition the speed of the systemis limited by the sampling circuitry.

[0010] Finally, a few published solutions, like U.S. Pat. No. 6,031,477and D. A. Mercer, L. Singer: “12-bit 125MSPS CMOS D/A Designed ForSpectral Performance”, International Symposium on Low Power Electronicsand Design, 1996, pp. 243-246, focus on improving the timing accuracy inthe single current switch circuits. With these methods, however, thereremains some finite signal frequency dependent distortion.

SUMMARY OF THE INVENTION

[0011] It is an object of the invention to reduce distortion in theoutput of a segmented current steering D/A converter.

[0012] The object is reached on the one hand by a digital-to-analogconverter comprising a first and a second current output, at least twocurrent sources, the currents of the current sources being summed toform an analog output signal, and assigned to each of the currentsources a current switch circuit for connecting the respective currentsource to the first current output if the current source is selectedaccording to a digital input signal and for connecting the respectivecurrent source to the second current output if the current source is notselected according to the digital input signal, each current switchcircuit comprising means for creating two overlapping complementarycontrol signals out of a signal indicating whether the current source isselected, while in a first group of the current switch circuits theconnection of the respective current source to the first current outputis controlled by the first one of the overlapping control signals andthe connection of the current source to the second current output iscontrolled by the second one of the overlapping control signals, andwhile in a second group of the current switch circuits the connection ofthe respective current source to the first current output is controlledby the second one of the overlapping control signals and the connectionof the current source to the second current output is controlled by thefirst one of the overlapping control signals, each of the current switchcircuits of the second group comprising in addition means for invertingthe signal input to the means for creating two overlapping complementarycontrol signals.

[0013] On the other hand, the object is reached by a method for reducingharmonic distortion in a digital-to-analog converter comprising a firstand a second current output, at least two current sources, the currentsof the current sources being summed up to form an analog output signal,and assigned to each of the current sources a current switch circuit forconnecting the respective current source to the first current output ifthe current source is selected according to a digital input signal andfor connecting the respective current source to the second currentoutput if the current source is not selected according to the digitalinput signal, the method comprising

[0014] creating for each current source of a first group of currentsources two overlapping control signals based on a signal indicatingwhether the respective current source is selected, and using the firstof said overlapping control signals for controlling the connection ofthe current source to the first current output and the second of saidoverlapping control signals for controlling the connection of thecurrent source to the second current output; and

[0015] creating for each current source of a second group of currentsources two overlapping control signals based on a signal which isinverted compared to the signal indicating whether the respectivecurrent source is selected, and using the first of said overlappingcontrol signals for controlling the connection of the current source tothe second current output and the second of said control signals forcontrolling the connection of the current source to the first currentoutput.

[0016] According to the invention, a certain number of current switchcircuits assigned to the current sources of a D/A converter is dividedinto two groups. The first group switches the respective current sourceto a first or a second current output conventionally. To this end, thecurrent switch circuits create overlapping control signals out of aninformation indicating whether the current source is presently selected.The current switch circuits of the second group, however, are modified.The connection of the outputs of the means for creating overlappingsignals to the actual switching means is switched. Additionally, thesignal entering the means for creating overlapping signals is inverted.As a result, the connections between the current source and the firstand the second current output are controlled with signals of the samestate as if a current switching circuit of the first group wereemployed, when disregarding the overlaps. The asymmetry of the overlaps,however, is changed.

[0017] Since part of the state changes now occur in a complementary wayas compared to the other part of the state changes, the asymmetricalglitches occurring during the state changes in the switches arecompensated in the summed up analog output signal. This means that thedistortion caused by the pulse relation errors in the control signalsspreads to the noise floor or at least decreases significantly.

[0018] It is an advantage of the invention that is does not necessitatean increase in the current consumption. Nor is the circuit complexityincreased, since only an inverter has to be added to realize themodified current switch cells. Another significant advantage is given bythe fact that there is no signal frequency dependency of thecompensation according to the invention.

[0019] Preferred embodiments of the invention become apparent from thesubclaims.

[0020] Many D/A converters comprise weighted, in particularbinary-weighted, current sources for converting the least significantbits (LSB) of a digital signal and unweighted current sources forconverting the most significant bits (MSB) of a digital signal. In sucha converter it is preferred that only the current switch circuitsassigned to the unweighted current sources are divided into two groupsfor a complementary controlling of the connection of the current sourcesto a first and a second current output. The weighted current sources arecontrolled conventionally, because they have different impacts on theresulting asymmetry.

[0021] Preferably, the two groups of current switch circuits arebasically of equal size in order to achieve an optimal compensation.

[0022] In an advantageous embodiment of the invention, two parallelarrays of current sources are employed. These two arrays are usedsimultaneously, i.e. with each change of state (at least) one currentsource of each array is switched at the same time. The current switchcircuits assigned to the current sources of the first array all belongto the first group, the current switch circuits assigned to the currentsources of the second array all belong to the second group of currentswitch circuits. Accordingly, in every switch transition both a modifiedand an unmodified cell switches at the same time. This leads to an evenbetter compensation of the asymmetries, since the compensation takesplace immediately and exactly matched with each switch and since anuneven distribution of carried out switches is irrelevant in thisimplementation. Moreover, this embodiment of the invention is alsosuitable for including the weighted current sources in the compensation,since the asymmetries caused by the switching of a current source in thefirst array are always compensated by the switching of an equal currentsource of the second array.

[0023] The digital-to-analog converter and the method according to theinvention are especially suited to be used in base stations and radiorelay transmitters.

BRIEF DESCRIPTION OF THE FIGURES

[0024] In the following, the invention is explained in more detail withreference to drawings, of which

[0025]FIG. 1 shows the general structure of a segmented current steeringD/A converter;

[0026]FIG. 2 shows the simulated spectrum of an output signal of a10-bit D/A converter without compensation;

[0027]FIG. 3a shows a known current switch employed in an embodiment ofthe invention;

[0028]FIG. 3b shows a modified current switch employed in an embodimentof the invention;

[0029]FIG. 4 shows the switching order of a 6-bit block of currentsources in an embodiment of the invention;

[0030]FIG. 5 shows a simulated spectrum of an output signal of a 10-bitD/A converter with compensation according to the invention;

[0031]FIG. 6 shows a simulated spectrum of an output signal of a 13-bitD/A converter without compensation; and

[0032]FIG. 7 shows a simulated spectrum of a 13-bit D/A converter withcompensation according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0033] The segmented current steering D/A converter of FIG. 1 and thespectrum of the output signal of FIG. 2 have already been describedabove. The 10-bit D/A converter of FIG. 1 is also the basis for thedescribed embodiment of the invention.

[0034]FIGS. 3a and 3 b schematically show a fist and a second currentswitch cell in a current steering D/A converter of FIG. 1. In bothcells, a current switch circuit is used for the steering of one of thecurrent sources 1 of the MSB-block of FIG. 1 by controlling adifferential switch pair S.

[0035] Each of the current sources 1 of the MSB block of FIG. 1 isdestined to output a differential current depending on the 6-bit MSBpart in a digital signal that is to be converted into an analog signal.One example of determining the switching order of the current sources 1can be taken from FIG. 4, in which each of the 63 current sources isdefined as a cell in a matrix by a pair of a column 1-8 and a row 1-8.Each of the current sources 1 belonging to columns 8, 6, 4 and 2 in FIG.4 is connected by a first current switch circuit according to FIG. 3a toone of the current outputs OUT, XOUT. Each of the current sources 1belonging to one of columns 1, 3, 5 and 7 in FIG. 4 is connected by asecond current switch circuit according to FIG. 3b to one of the currentoutputs OUT, XOUT. The cells corresponding to the latter current sources1 are marked with an X in FIG. 4. The 6-bit MSB signals can be decodedinto 64 thermometerly decoded signals. These 64 signals can then controlall 63 switching cells.

[0036] In FIG. 3a, an input line providing an input signal IN isconnected the input of a D-flipflop 4 which receives additionally at itstiming input a clock signal CLK. The two complementary output signals ofthe D-flipflop Q and QZ are input to a latch circuit 5 the output linesof which are both connected to a respective inverter 6, 7. The output ofeach of the inverters 6, 7, finally, is coupled to the base of one oftwo transistors 8, 9 forming a differential switch pair S. Thetransistors 8, 9 are suitable to connect a current source 1 to one oftwo different current outputs OUT and XOUT respectively.

[0037] The current switch circuit of FIG. 3a is used for steering halfof the current sources 1 of the MSB block of FIG. 1 and works asfollows:

[0038] The input signal IN indicates in accordance with the 6 bit MSBpart of the present 10-bit digital signal whether a current source hasto be selected to provide a current. If the current source is to beselected, a high input signal IN is input to the D-flipflop 2, otherwisea low input signal IN. The D-flipflop 2 synchronizes the signal IN withthe rising edge of the clock signal CLK and outputs the synchronizedsignal Q and a complimentary synchronized signal QZ. The synchronizedsignal Q and complementary synchronized signal QZ are fed to the latchcircuit 3 and the inverters 4, 5 which are used to generate overlappingcontrol signals for the transistors 6, 7 of the differential switch pairS.

[0039] The differential switch pair S connects the current source 1 toone of the current outputs OUT and XOUT according to the overlappingcontrol signals. Since the control signals are overlapping, theconnection of the current source 1 to one or the other of the currentoutputs OUT, XOUT is overlapping as well, i.e. for a short period oftime after each switch, the current source 1 is connected to bothcurrent outputs OUT, XOUT in parallel. This way a period of time withoutconnection to one of the current outputs OUT, XOUT because of timingdelays in one of the control signals is prevented. That means that theswitching waveforms are overlapping in order to prevent the currentsource to drop out of its saturation region. The overlaps are differentfor the two switching direction OUT to XOUT and XOUT to OUT which leadsto the harmonic distortions described with reference to the state of theart and depicted in the simulated spectrum of FIG. 2, if the currentswitch circuit of FIG. 3a is employed for all current sources 1 of theD/A converter.

[0040] The current switch circuit of FIG. 3b comprises the same elements2-7 as the current switch circuit of FIG. 3a. In addition, an inverter 8is inserted between the input line and the input of the D-flipflop 2.Moreover, the overlapping control signals generated by the latch circuit3 and the inverters 4, 5 are each fed to the opposite transistors 7, 6as compared to FIG. 3a.

[0041] The current switch circuit of FIG. 3b works analogously to thecurrent switch circuit of FIG. 3a, except that instead of the inputsignal IN, an inverted signal D is fed to the D-flipflop 2 and that theoverlapping control signals control the opposite transistors 7, 6 of thedifferential switch pair S as compared to FIG. 3a. As a result of theinversion of the input signal IN on the one hand and the changed accessof the overlapping control signals to the differential switch pair S onthe other hand, the differential switch pair S is basically controlledby signals of the same value as in FIG. 3a. And also in a current switchcircuit of FIG. 3b, the overlaps of the overlapping control signals areasymmetric. But the lengths of the overlaps for a switch from currentoutput OUT to current output XOUT and from current output XOUT tocurrent output OUT are exchanged compared to the lengths of the overlapsof the overlapping control signals in FIG. 3a.

[0042] Therefore, when employing a current switch circuit of FIG. 3a forhalf of the current sources 1 of the MSB block and a current switchcircuit of FIG. 3b for the other half of the current sources 1 of theMSB block, half of the state changes occur into complementary directionas the rest. As a result, the distortion caused by the pulse relationerrors in the control signals spreads into the noise floor.

[0043]FIG. 5 shows a simulated spectrum of a 10-bit D/A converter ofFIG. 1 employing the control switch circuits of FIGS. 3a and 3 b for the63 current sources of the 6-bit MSB block, the sampling rate being 200MHz and the signal frequency 20 MHz. The different control switchcircuits were distributed to the current sources as indicated in FIG. 4.The output voltage V_(out) of the D/A converter is depicted over thefrequencies of the generated analog output.

[0044] When comparing the spectrum of FIG. 5 with the spectrum of FIG. 2which is based on the same 10-bit D/A converter except that a currentswitch circuit of FIG. 3a was used for all current sources 1 of the6-bit MSB block, the improvement is obvious. The 2^(nd) harmoniccomponent cannot be distinguished anymore from the noise floor and the3^(rd) harmonic component which is now dominating limits the SFDR from53 dB to 59 dB.

[0045] There is still some distortion left due to the uncompensatedbinary-weighted 4-bit LSB block.

[0046] The compensation is simple and does not increase the complexityof the circuit and it can easily be transferred to higher resolutionconverters. For high resolution converters two or more unweightedcurrent source arrays can be used.

[0047] The compensation of asymmetries according to the invention wasalso tested in a 13-bit D/A converter with a 7-bit MSB part to verifyits suitability in high-resolution D/A converters.

[0048]FIG. 6 shows the simulated spectrum of a 13-bit D/A converterwithout compensation. The sample rate was 67 MHz and the signalfrequency 5.5 MHz. As can be seen in the figure, the dominating 2^(nd)harmonic component is down 56 dB from the main signal.

[0049]FIG. 7 shows in contrast the simulated spectrum of a 13-bit D/Aconverter with a compensation according to the invention. The 3^(rd)harmonic component is now dominating with an SFDR of 67 dB, the 2^(nd)harmonic component being reduced to an SFDR of 80 dB. Accordingly, itwas possible to achieve a significant improvement with the compensationaccording to the invention also in a 13-bit D/A converter, even thoughthe used converter was not designed optimally for high-speedapplications and even though there was again no compensation for the 4current sources responsible for the 4-bit LSB part of the digitalsignals.

1. Digital-to-analog converter comprising a first and a second currentoutput (OUT,XOUT), at least two current sources (1), the currents of thecurrent sources (1) being summed to form an analog output signal, andassigned to each of the current sources (1) a current switch circuit forconnecting the respective current source (1) to the first current output(OUT) if the current source is selected according to a digital inputsignal and for connecting the respective current source (1) to thesecond current output (XOUT) if the current source (1) is not selectedaccording to the digital input signal, each current switch circuitcomprising means (4, 5, 6, 7) for creating two overlapping complementarycontrol signals out of a signal (IN) indicating whether the currentsource (1) is selected, while in a first group of the current switchcircuits the connection of the respective current source (1) to thefirst current output (OUT) is controlled by the first one of theoverlapping control signals and the connection of the current source (1)to the second current output (XOUT) is controlled by the second one ofthe overlapping control signals, and while in a second group of thecurrent switch circuits the connection of the respective current source(1) to the first current output (OUT) is controlled by the second one ofthe overlapping control signals and the connection of the current source(1) to the second current output (XOUT) is controlled by the first oneof the overlapping control signals, each of the current switch circuitsof the second group comprising in addition means (10) for inverting thesignal (IN) input to the means for creating two overlappingcomplementary control signals (4, 5, 6, 7).
 2. Digital-to-analogconverter according to claim 1, characterized in that each currentswitch circuit comprises further a clock input for inputting a clocksignal (CLK) and a means (4) for synchronizing the signal (IN,D)indicating whether the respective current source (1) is selected withthe clock signal (CLK), before providing it to the means for creatingtwo overlapping complementary control signals (4, 5, 6, 7). 3.Digital-to-analog converter according to claim 2, characterized in thatthe means (4) for synchronizing the signal (IN,D) indicating whether thecurrent source (1) is selected with the clock signal (CLK) outputs asynchronized signal (Q) and a complementary synchronized signal (QZ),while the two overlapping complementary control signals are created outof the synchronized signal (Q) and the complementary synchronized signal(QZ).
 4. Digital-to-analog converter according to claim 2 or 3,characterized in that the means for synchronizing (4) is a D-flipflopreceiving at its signal input a signal (IN,D) indicating whether therespective current source (1) is selected and at its clock input a clocksignal (CLK) equal for all current switch circuits of thedigital-to-analog converter, the D-flipflop synchronizing said signal(IN,D) with the rising edge of the clock signal (CLK). 5.Digital-to-analog converter according to one of the preceding claims,characterized in that the means for creating two overlappingcomplementary control signals is a latch circuit (5) with an inverter(6, 7) connected to each of its outputs.
 6. Digital-to-analog converteraccording to one of the preceding claims, characterized in that thecurrent switch circuits divided into a first group and a second groupare assigned to unweighted current sources (1).
 7. Digital-to-analogconverter according to one of the preceding claims, characterized byunweighted and weighted current sources, wherein only the current switchcircuits assigned to the unweighted current sources (1) are divided intoa first group and a second group.
 8. Digital-to-analog converteraccording to one of the preceding claims, characterized in that thenumber of current switch circuits of the first group and of the secondgroup is basically the same.
 9. Digital-to-analog converter according toone of the preceding claims, characterized by a double array of currentsources (1), the current sources (1) of one array being switched by thefirst group of current switch circuits and the current sources (1) ofthe other array being switched by the second group of current switchcircuits, each current source (1) of one of the arrays being switchedsimultaneously to one current source (1) of the other array. 10.Digital-to-analog converter according to one of the preceding claims,characterized by being an integrated digital-to-analog converter. 11.Base station comprising a digital-to-analog converter according to oneof claims 1 to
 10. 12. Radio relay transmitter comprising adigital-to-analog converter according to one of claims 1 to
 10. 13.Method for reducing harmonic distortion in a digital-to-analog convertercomprising a first and a second current output (OUT, XOUT), at least twocurrent sources (1), the currents of the current sources (1) beingsummed up to form an analog output signal, and assigned to each of thecurrent sources (1) a current switch circuit for connecting therespective current source (1) to the first current output (OUT) if thecurrent source (1) is selected according to a digital input signal andfor connecting the respective current source (1) to the second currentoutput (XOUT) if the current source (1) is not selected according to thedigital input signal, the method comprising creating for each currentsource (1) of a first group of current sources two overlapping controlsignals based on a signal (IN) indicating whether the respective currentsource (1) is selected, and using the first of said overlapping controlsignals for controlling the connection of the current source (1) to thefirst current output (OUT) and the second of said overlapping controlsignals for controlling the connection of the current source (1) to thesecond current output (XOUT); and creating for each current source (1)of a second group of current sources two overlapping control signalsbased on a signal (D) which is inverted compared to the signal (IN)indicating whether the respective current source (1) is selected, andusing the first of said overlapping control signals for controlling theconnection of the current source (1) to the second current output (XOUT)and the second of said control signals for controlling the connection ofthe current source (1) to the first current output (OUT).